• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A noise reduction circuit and method are described for implementation in a delta modulation system for signal transmission. Under certain conditions when the delta modulator has selected the minimum step size for encoding and transmission, the present technique and apparatus are effective to change the minimum step size in a way which prevents low level noise generation from occurring in the delta modulation system. The technique and circuit can be utilized with most commonly available delta modulators which have means for changing the step size (i.e., the delta) but is used to the best effect on more stable implementations of delta modulators where an integrator is replaced by a digital accumulator and a digital-to-analog converter.
    公开号:SU1082343A3
    申请号:SU782677104
    申请日:1978-10-16
    公开日:1984-03-23
    发明作者:Джордж Крауз Вильям
    申请人:Интернэшнл Бизнес Машинз Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

     The invention relates to radio engineering and can be used in installations for transmitting information with a step size generator. A companded delta modulation device is known, comprising a series-connected comparison unit and a trigger, the output of which is connected via an integrator to the first input of the comparison unit, and a clock generator lj is connected to another trigger input and another input of the integrator. However, the known device has a high noise level. The purpose of the invention is to reduce the noise level. The goal is achieved by the fact that a companded delta modulation device containing a series-connected comparison unit and a trigger, the output of which is connected through the integrator to the first input of the comparison unit, and a different clock generator is connected to another trigger input and another integrator input. a compander of signals and a node for converting signals, the trigger output is connected to the input of the generator of companding signals and the first input of the computer conversion unit diruyuschih second signal input connected to the output of the generator kompandiruyuschih signals, the additional WMOs integrator connected to the output node kompandiruyuschih conversion signals, a third input coupled to a clock generator. FIG. 1 shows a structural electrical circuit of the proposed device, FIG. 2 shows an embodiment of a node for converting companding signals; FIG. Zi4 voltage plots that show the operation of the device. The device for companded delta modulation contains a comparison unit 1, a generator of 2 clock pulses, a trigger 3, an integrator 4, consisting of a digital-analog converter 5 and a digital accumulating adder 6, a generator of 7 compander signals, a node 8 of converting compander signals, containing a block 9 comparisons (Fig. 2), shift register 10, first second, third and fourth elements AND 11-14 respectively, first, second and third elements OR 15-17 respectively, first and second inverters 18 and 19, respectively. The device works as follows. An analog signal from a microphone or similar source is supplied to Comparison Unit 1. The output of this block is fed to trigger 3, which, based on the match signal, stores at the clock input the actual instantaneous value of the read value. The digital accumulator 6 and the digital-to-analog converter 5 work together and represent the integrator 4, which is typical for delta modulation. The output signal of the digital-analog converter 5 is fed to the input of the comparison unit 1. In this way, the output signal of comparator 1 gives the polarity of the difference between the input analog signal and the output value of the digital-analog converter 5. This polarity, in the form of a read value, is remembered by trigger 3 by the control action of the clock signal at the input. Trigger 3 gives a delta-modulated binary output signal Dj. Generator 7 calculates, for each value read, the required step size, based on a predetermined algorithm, necessary to obtain a companded step value in accordance with the previous predetermined voltage curve. The pitch value is fed to the accumulated adder 6, where it is added to or subtracted from the value generated by the adder. In the present embodiment, node 8 is additionally added between the generator and accumulating adder 6. In accordance with the algorithm provided for in generator 7, the calculated step size must pass through node 8 and be modified in accordance with the invention. The output of trigger 3 controls the addition and subtraction in accumulative adder 6. If comparator unit 1 detects that the output of D / A converter 5 is less than the input analog signal, then the step size is added to the magnitude of the signal in accumulator adder 6. If the output signal of the digital-to-analog converter is larger than the input analog signal, then the comparator sets the trigger to the position instead of the O position, as a result of which the step size of the generator 7 is subtracted from the value of drove in accumulator 6 generator 7 calculates a desired step size in accordance with an algorithm contained therein companding, which for its part is not essential to the invention. It is important, however, that the companding step size algorithm provides the minimum step size and provides devices that recognize when the minimum step size is reached. The analog input signal, together with the rectangular pulses of the accumulating adder, next to the read frequency, is shown in FIG. Behind. When the value of the analog signal approaches the signal of the accumulating adder, one step occurs in the positive or negative direction, depending on the difference between the analog signal and the signal of the accumulating adder. This process takes place with control from the side of the generator 7. If, for example, as shown at point X in FIG. For, the analog signal supposedly reaches such a value that corresponds to the accumulating adder signal at the moment of reading, then an additional zero appears that interrupts the series, from successively alternating ones and zeros characteristic of a typical rest signal, and shifts up the accumulating adder signal to such the value that corresponds to the minimum step of the generator 7. Above this (at the output of the demodulator, at the other end of the signal transmission section), a signal with an increased amplitude instead of a normal rest signal. The frequency of such sporadically occurring deviations is small, but lies in the range of sound frequencies that pass through the usual 434 no. Low frequency filter used, which serves to filter out the components of the reading frequency. This phenomenon, as shown at point Y in FIG. Pros, can repeat at sporadic intervals and leads to promiscuity of transmission if the accumulator signal, as shown at points Z, passes near the level of the quiescent signals. In this case, additional steps may occur in one direction or another, instead of the usual undistorted series of ones and zeros. The resulting series of binary signals is shown in FIG. 36. The initial undistorted transmission of quiescent signals, consisting of alternating ones and zeros, at point X and at further points Y, Z, etc. interrupted by a series of more or less random signals. At the same time, undesirable noise components appear, although with a low level, but in the audio frequency range, and this noise is heard behind the demodulator. The increment value calculated by generator 7 is supplied to node 8 as a coded series of binary signals, in which the binary signal O is the maximum value and the binary signal 8 is the minimum value. The binary signals from O to 6, without changes, pass to the accumulating adder. Binary signals from O to 7 are analyzed by means of the first element OR 15, the output of which comes in the form of binary 1, if the input signal on the binary lines from O to 7 is 1. This step size, coming from generator 7, is greater than the specified minimum value, so it does not need to be modified by means of a modifying device when transmitting the step value to the accumulator. This task is solved by the output signal of the first element OR 15, which is used as a preparatory link before the two elements AND 13 and 14, which pass the binary signals 7 and 8 through the elements OR 17 and 16 without changing them to the accumulating adder. The output signal of the first element OR 15
    is inverted by the second inverter 19, the output of which, under the specified conditions, again blocks the elements 11 and 12, and both these elements give a binary signal O to the elements 16 and 17 and do not prevent the passage of the binary signals 7 and 8.
    If the binary signal 8 is to be transmitted from the generator 7 as the binary value 1, then the modifying device should start working and change the values of the steps entered into the accumulating adder. This critical condition is recognized by the first element OR 15 and, by means of the output signal from the last, is turned into state O. The signal O coming from the first element OR 15 prevents the binary signals 7 and 8 from passing through the elements 14 and 13 directly to the elements OR 17 and 16. At the same time, the signal O from the first element OR 15 is inverted in the second inverter 19 and the elements 11 and 12 are prepared. As a result, signal 1 from the output of the comparison block 9 is transmitted through the first on the inverter 18 and through the first element AND 11 and the third element OR 17 is transmitted to the output line of the binary signal 8. Under these conditions, the values of all steps transmitted to the accumulating adder are detected in all binary positions from 0 to 6 for the signal O, In the same way, signal O is transmitted in binary position 7 from the output of the reference unit, but in this case, signal 1 is transmitted in binary position 8. In the following, shift register 10 shifts by one binary unit. Each time a clock is read, the last transmitted delta modulation signal is generated by this shift register, while a new binary signal is supplied from trigger output 3. The abbreviation Dj is used to indicate the most recent binary delta modulation signal, and Dj is denoted by the preceding binary delta modulation signal. During each clock cycle η, the signals are fed together to the input of comparator block 9, the output of which, in the form of a binary signal 7 or 8, determines the step size transmitted to the accumulating adder.
    The table below shows the output values for binary signals 7 and 8 depending on the binary signals D and 0 "delta modulation
    In this table, the values of output binary signals 7 and 8 are given as a function of BP and D. when the binary signals from O to 7 collectively determine the level of O and the modification should work. If the binary signals from O to 7 do not all determine O, then the binary signals from O to 8 are transmitted as they arrive, and in this case, node 8 does not work.
    On. FIG. 4a and 4b show the results of this method.
    When the calculated value corresponds to the minimum step size, and the new binary signal of the delta modulation is not equal to the previous signal, then the double value of the minimum step size is applied to the accumulating adder as in the step size (Fig. 4a). The result of this modification is an automatic adjustment of the step size in order to stretch the signal level. FIG. 4a, the rectangular signals of the accumulating adder are doubled, as soon as the point X is reached and the accumulating adder signal is equal to or less than the analog signal, the minimum step size is obtained and the double signal O is transmitted, which interrupts the preceding series of alternating zeros and
    units. In the subsequent cycle, the minimum step size is doubled again, followed by a series of alternating zeros and ones again. Thus, the signal of the accumulating adder is changed to stretch the level of the signal at rest, which eliminates unwanted noise signals, which, as shown in FIG. 3 might occur.
    F (1g.2
    Analog signal
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    1082343
    Voltage accumulating adder
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    Sporadic
    Seri dS0u4Hbin signals
    Fig.Z
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    Fme.Ch
    权利要求:
    Claims (1)
    [1]
    DEVICE FOR COMPANDED DELTA-MODULATION, containing a series-connected comparison unit and a trigger, the output of which is connected through the integrator to the first input of the comparison unit, and a clock generator connected to the other input of the trigger and another input of the integrator is not connected I mean that, in order to reduce the noise level, a compander signal generator and a compander signal conversion unit have been introduced, and the trigger output is connected to the input of the compander signal generator and the first input of the node eobrazovaniya kompandiruyuschih signals, the second input of which .soedinen yield kompandiruyuschih oscillator signals and the additional integrator input coupled to the output node kompandiruyuschih conversion signal, a third input coupled to a clock generator.
    Figure 1 ^ C- "" 1.082343
    类似技术:
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    同族专利:
    公开号 | 公开日
    FR2406346B1|1983-03-18|
    IT1159131B|1987-02-25|
    DE2836049C2|1985-01-31|
    FR2406346A1|1979-05-11|
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    GB1576980A|1980-10-15|
    JPS5462765A|1979-05-21|
    CA1121057A|1982-03-30|
    ATA611778A|1984-03-15|
    AU3912378A|1980-02-28|
    JPS5919491B2|1984-05-07|
    DE2836049A1|1979-04-26|
    ES474225A1|1979-04-01|
    CH643973A5|1984-06-29|
    IT7828126D0|1978-09-27|
    AU517906B2|1981-09-03|
    US4110705A|1978-08-29|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US3716803A|1971-12-27|1973-02-13|Bell Telephone Labor Inc|Stabilized delta modulator|
    US3806806A|1972-11-20|1974-04-23|Bell Telephone Labor Inc|Adaptive data modulator|
    JPS547525B2|1973-12-28|1979-04-07|
    US4025852A|1975-10-14|1977-05-24|Bell Telephone Laboratories, Incorporated|Method and arrangement for controlling delta modulator idle-channel noise|DE2849001C2|1978-11-11|1982-10-07|TE KA DE Felten & Guilleaume Fernmeldeanlagen GmbH, 8500 Nürnberg|Network for adaptive delta modulation|
    US4264974A|1979-12-17|1981-04-28|International Business Machines Corporation|Optimized digital delta modulation compander having truncation effect error recovery|
    US4700362A|1983-10-07|1987-10-13|Dolby Laboratories Licensing Corporation|A-D encoder and D-A decoder system|
    NO160750C|1985-06-27|1989-05-24|Norway Geophysical Co|DEVICE FOR DIGITAL SIGNAL PROCESSING ON CONTINUOUS BIT FLOWS.|
    US5592508A|1994-09-22|1997-01-07|Cooper; J. Carl|Analog signal coding and transmission apparatus and method capable of operation with multiple types of analog and digital signals|
    US9503121B2|2014-10-17|2016-11-22|Infineon Technologies Ag|Very high dynamic-range switched capacitor ADC with large input impedance for applications tolerating increased distortion and noise at large input signal levels|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US05/842,710|US4110705A|1977-10-17|1977-10-17|Noise reduction method and apparatus for companded delta modulators|
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